The present invention relates to the design of integrated circuits and in particular to the creation of netlists from schematics for the simulation of such schematics.
Computer-aided engineering and manufacturing (CAE/CAM) technology consists of software tools that assist in the production of integrated circuits (ICs). Production of an IC begins by representing the circuit design as a schematic. Schematics consist of symbol instances connected by nets which demonstrate the functional design of the circuit. Symbol instances are pictorial icons that represent a complete functional block. Symbol instances can be primitive elements (such as transistors and resistors), abstractions of combinations of primitive elements (such as NAND gates and NOR gates), or higher level groupings of these various elements.
Netlists are a secondary representation of a circuit design. A netlist is a text file describing the circuit. The netlist lists all of the symbol instances and their connecting nets within a schematic. CAE software can be used to translate a schematic into a netlist.
A netlist is used as input to a simulator, another CAE tool. Simulators use netlists and other input files to imitate the function of the circuit design before the design is incorporated in hardware. Simulating a circuit is an efficient and cost effective method of testing a circuit. However, simulating a portion of the circuit design is problematic. One primary problem is that the circuits often contain several million individual instances connected by several million nets. The complexity of such a large structure, even when processed by a powerful computing system, cannot be simulated in its entirety by the simulator. Instead, a portion of the circuit design must be isolated for simulation. Some present systems allow only a portion to be simulated. For example, simulation software from Cadence Design Systems, Inc. of San Jose, Calif., utilizes the n1Action command. The n1Action command is used to xe2x80x9cignorexe2x80x9d a portion of the circuit while simulating other portions of the circuit.
A secondary problem arises in connection with simulating just a portion of the circuit. A partial simulation is not accurate since the load on the simulated portion may depend on circuitry which is not currently being simulated. When using simulation software from Cadence Design Systems, Inc., a testing engineer must estimate the load caused by ignored portions of the circuit and then the engineer must either add this estimated amount, by hand, to the results of the simulation, or may enter this estimate into the computer system and have the system itself add this estimated amount to the results.
What is needed is a way to simulate a portion of a circuit design, while tracking the load effects from the non-simulated portions of the design. This invention would need to offer a higher degree of accuracy than is currently achieved by the testing engineer""s estimation techniques in current systems. The invention would also need to be flexible so that changes to the schematic would cause the appropriate change to the load.
A method and device for automatically generating load circuits for a netlist. A computer system having a schematic for a circuit is used to create a netlist. While constructing the netlist, instances are checked for directives. The directives indicate that the instance should be tracked as a load circuit. For the instances having such a directive, the hierarchal portion of the circuit attached to the instances"" nets is flattened. The collected flat circuit replaces the instance in the netlist as a load circuit.